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data sheet august 1999 T7507 quad pcm codec with filters, termination impedance, and hybrid balance features n 5 v only n low-power, latch-up-free cmos technology: 37 mw/channel typical operating power dissipation 1 mw/channel typical powerdown dissipation n fixed master clock frequency: 2.048 mhz n on-chip sample and hold, autozero, and precision voltage reference n differential architecture for high noise immunity and power supply rejection n pcm interface: fixed 2.048 mhz data rate delayed and nondelayed pcm modes fully flexible time-slot assignment transmit and receive aligned or offset n transmit pcm data output enable n serial control interface with controlling processor n latched parallel control interface with slic and switch n meets or exceeds d3/d4 (as per lucent pub 43801) and itu-t g.711g.714 requirements n operating temperature range: C40 c to +85 c n a-law companding n hybrid balance and termination impedance: 200 w in series with 680 w || 0.1 f (peoples republic of china z t ) matched with l8567 slic n programmable receive gain (C3.5 db or C7 db), fixed transmit gain (0 db) when matched with l8567 slic n 44-pin plcc description the T7507 device is a single-chip, four-channel a-law pcm codec with filters. this integrated circuit provides analog-to-digital and digital-to-analog con- version. it provides the transmit and receive filtering necessary to interface a voice telephone circuit to a time-division multiplexed system. this device is pack- aged in a 44-pin plcc. this codec is intended for use with lucent technolo- gies microelectronics groups l8567 slic. when used with that slic, the line tip/ring pair is termi- nated in the network required for central office appli- cations in the peoples republic of china (prc). proper hybrid balance and transmit and receive gains are also obtained. this device uses a serial data control scheme to interface with the controlling processor. this device has a latched parallel data control scheme to provide control bits to, and receive status bits from, the slic and switch. this interface is designed to be compati- ble with the lucent l8567 slic and l7583 solid- state switch.
2 lucent technologies inc. data sheet august 1999 termination impedance, and hybrid balance T7507 quad pcm codec with filters, table of contents contents page features ......................................................................1 description...................................................................1 pin information ............................................................5 functional description .................................................7 pcm interface ........................................................7 analog interface .....................................................8 transmission levels...............................................8 microprocessor serial data control and l8567 slic/l7583 switch (or emr) control interfaces .............................................................8 enable transfers when cclk is bursted with csel ...........................................................9 enable transfers when cclk is not restricted to csel low.......................................9 input word definition............................................12 output word definition .........................................14 powerup ...............................................................14 T7507 ..............................................................14 output word....................................................14 en status ........................................................14 input wordpcm interface ............................14 input wordrelay control/timing .................14 input wordcontrol mode .............................14 state definitions ...................................................14 powerup ..........................................................14 standby ...........................................................14 full-chip powerdown ......................................14 absolute maximum ratings.......................................15 handling precautions ................................................15 electrical characteristics ...........................................15 dc characteristics.................................................15 transmission characteristics ....................................16 ac transmission characteristics ..........................17 overload compression ...................................18 chip set performance specifications ........................21 gain......................................................................21 gain flatnessin band .......................................21 gain flatnessout of bandhigh frequencies .......................................................21 gain flatnessout of bandlow frequencies .......................................................22 loss vs. level relative to loss at C10 dbm input at 1020 hz ................................................22 return loss ..........................................................22 hybrid balance .....................................................22 microprocessor interface ...........................................23 timing characteristics ...............................................25 applications ...............................................................28 outline diagram.........................................................29 44-pin plcc ........................................................29 ordering information..................................................30 figures page figure 1. block diagram ............................................ 4 figure 2. pin diagram................................................. 5 figure 3. typical analog input section ...................... 8 figure 4. overload compression ............................. 18 figure 5. termination impedance ............................ 21 figure 6. transmit and receive direction frequency-dependent loss relative to gain at 3400 hz ................................... 21 figure 7. loss vs. level ........................................... 22 figure 8. return loss .............................................. 22 figure 9. hybrid balance ......................................... 22 figure 10. slic/switch interface timing ................. 24 figure 11. microprocessor interface write timing .................................................... 24 figure 12. T7507 transmit and receive timing, fsep = 1 mclk or ifs = 1, delayed timing (d0 = 0) ...................................... 26 figure 13. T7507 transmit and receive timing, fsep = 1 mclk or ifs = 1, nondelayed timing (d0 = 1) ...................................... 26 figure 14. T7507 receive timing, fsep > 1 mclk and ifs = 0, delayed timing (d3 = 0) .................................................. 27 figure 15. typical frame sync timing (ifs = 0) ..... 27 figure 16. basic loop start application using the T7507 and the l7583 switch for 200 w + (680 w || 100 nf) complex termination and hybrid balance ............ 28
lucent technologies inc. 3 data sheet august 1999 termination impedance, and hybrid balance T7507 quad pcm codec with filters, table of contents (continued) tables page table 1. pin descriptions .................................................................................................... ....................................5 table 2. microprocessor interface descriptions ............................................................................... .....................11 table 3. c0, c1 channel select ................................................................................................ .............................12 table 4. m, d4, d3, d2, d1, d0 mode select and data ........................................................................... ..............12 table 5. m = 0 mode (pcm time-slot assignment) ................................................................................ ...............12 table 6. m = 1, d4 = 0 mode (relay state control and delayed/nondelayed timing) .........................................13 table 7. m = 1, d4 = 1 mode (codec state control and slic state control) ..................................................... ..13 table 8. digital interface ................................................................................................... ....................................15 table 9. power dissipation .................................................................................................... ................................16 table 10. analog interface ................................................................................................... .................................16 table 11. absolute gain ...................................................................................................... ..................................17 table 12. gain tracking ....................................................................................................... ..................................17 table 13. distortion .......................................................................................................... ......................................17 table 14. envelope delay distortion .......................................................................................... ...........................18 table 15. decoder limits relative to gain at 1020 hz ........................................................................... ................19 table 16. encoder limits, includes effect of termination impedance filter relative to gain at 1020 hz ..............19 table 17. termination impedance limits relative to gain at 1020 hz ............................................................. ......19 table 18. hybrid path limits relative to gain at 1020 hz ....................................................................... ...............19 table 19. noise .............................................................................................................. .......................................20 table 20. interchannel crosstalk (between channels) .......................................................................... ...............20 table 21. gain ................................................................................................................ ........................................21 table 22. gain flatnessin band ............................................................................................... ..........................21 table 23. gain flatnessout of bandlow frequencies .......................................................................... ........22 table 24. T7507 microprocessor interface timing ............................................................................... ..................23 table 25. clock section ........................................................................................................ ..................................25 table 26. T7507 transmit section (delayed timing).............................................................................. ................25 table 27. T7507 transmit section (nondelayed timing)........................................................................... .............25 table 28. T7507 receive section ............................................................................................... ...........................25
4 lucent technologies inc. data sheet august 1999 termination impedance, and hybrid balance T7507 quad pcm codec with filters, description (continued) 5-3579.a(f) figure 1. block diagram vf x in1 vf r on1 vf r op1 vf x in0 vf r on0 C + bandpass encoder channel 0 decoder pcm powerdown internal timing bias channel 1 channel 2 channel 3 low-pass d x d r fsep ifs d x en gndd mclk cclk v dd (2) gnda (4) z t hybal vf r op0 vf x in2 vf r on2 vf r op2 vf x in3 vf r on3 vf r op3 di do csel en0 c en1 c en2 c en3 c rd1 c rd2 c rd3 c b0 c b1 c nstat c ntsd c ntsd0 ntsd1 ntsd2 ntsd3 slic & filter network filter network control interface & control circuitry & reference switch control interface
lucent technologies inc. 5 data sheet august 1999 termination impedance, and hybrid balance T7507 quad pcm codec with filters, pin information 5-5347a(f) figure 2. pin diagram table 1. pin descriptions pin symbol type name/function 1 fsep i d frame sync separation. the pulse width of this 8 khz signal defines the timing offset between the transmit and receive frames. if the ifs pin is 0, internally generated receive frame sync pulses are delayed from the corresponding transmit frame sync pulse rising edge by one less than the fsep pulse width in negative mclk edges. if the pulse width is one mclk period or less or if ifs is high, the transmit and receive frame syncs are made coincident. loss of fsep causes the device to power down. a delay of 255 clock pulses is not allowed. timing relationships between fsep and time slot 0 are given in figures 1214. this input is also the frame sync for all the codec filters and pcm inter- face timing generated from mclk. an internal pull-down is on fsep. 2 gndd digital ground. ground connection for the digital circuitry. all ground pins must be con- nected on the circuit board. 3 d x o transmit pcm data output. this pin remains in the high-impedance state except during active transmit time slots. an active transmit time slot is defined by programming, fsep, and the state of ifs. data is shifted out on the rising edge of mclk. 4 d r i receive pcm data input. the data on this pin is shifted into the device on the falling edges of mclk. data is only entered for valid time slots as defined by the relationship of the time-slot programming pulse on the fsep input, and the state of ifs. 5 mclk i master clock input. the frequency must be 2.048 mhz. this clock serves as the bit clock for all pcm data transfer. a 40% to 60% duty cycle is required. 6 dxen o transmit pcm data output flag. an open-drain output that pulses low during the period when the d x output is enabled. 39 38 37 36 35 34 33 32 31 30 29 ntsd0 ntsd1 ntsd3 ntsd2 en 0 c en 1 c en 3 c en 2 c v dd vf x in0 agnd0 ntsd c nstat c b1 c b0 c rd3 c rd2 c rd1 c v dd vf x in2 agnd2 vf r on2 7 8 9 10 11 12 13 14 15 16 17 T7507 6543 1 24443424140 25 18 20 21 22 26 27 19 28 24 23 d x en mclk d r d x gndd fsep ifs csel cclk di do vf r op2 vf r op3 vf r on3 agnd3 vf x in3 agnd1 vf x in1 vf r on1 vf r op1 vf r op0 vf r on0
6 lucent technologies inc. data sheet august 1999 termination impedance, and hybrid balance T7507 quad pcm codec with filters, pin information (continued) table 1. pin descriptions (continued) pin symbol type name/function 7 ntsd c i not thermal shutdown status inputl8567 slic. logic level status input from l8567 slic indicating if slic is in thermal shutdown or normal device operation. this input is accepted from the latched parallel data output of the slic and outputted on the serial data output bus do to the microcontroller. this pin is meant to be a shared output among the four channels associated with the quad T7507, using the en control to determine valid data among the four channels. 8 nstat c i not loop closure/not ring trip status input. logic level status input from l8567 slic indicating loop on-/off-hook status. this input is accepted from the latched parallel data output of the slic and outputted on the serial data output bus do to the microcon- troller. this pin is meant to be a shared output among the four channels associated with the quad T7507, using the en control to determine valid data among the four channels. 9 10 b1c b0c o slic state control. these logic level outputs control the state of the l8567 slic. these pins are meant to be a shared output among the four channels associated with the quad T7507, using the en control to determine valid data among the four channels. 11 12 13 rd3 c rd2 c rd1 c o driver control. these logic level outputs control the state of an electromechanical relay driver on the l8567 slic or a solid-state relay contact on the l7583 via the l7583 logic control inputs. these pins are meant to be a shared output among the four channels associated with the quad T7507, using the en control to determine valid data among the four channels. 14 31 v dd 5 v analog power supplies . both pins must be connected on the circuit board. each pin should be bypassed to ground with at least 0.1 f of capacitance as close to the device as possible. 22 15 24 30 vf x in3 vf x in2 vf x in1 vf x in0 i voice frequency transmitter input. analog inverting input to the noninverting opera- tional amplifier at the transmit filter input. connect the signal to be digitized to this pin through a capacitor c i (see figure 3). 21 16 23 29 agnd3 agnd2 agnd1 agnd0 analog grounds. all ground pins must be connected on the circuit board. 20 17 25 28 vf r on3 vf r on2 vf r on1 vf r on0 o voice frequency receiver negative output. this pin can drive 2000 w (or greater) loads. 19 18 26 27 vf r op3 vf r op2 vf r op1 vf r op0 o voice frequency receive positive output. this pin can drive 2000 w (or greater) loads. 39 38 36 37 ntsd0 ntsd1 ntsd2 ntsd3 i not thermal shutdown status inputl7583 switch. logic level status input from l7583 solid-state switch indicating if switch is in thermal shutdown or normal device operation. this input is accepted on a per-line basis from the four switches associated with the quad T7507, and outputted on the serial data output bus do to the microcontrol- ler. if unused, tie to ground or 5 v.
data sheet august 1999 lucent technologies inc. 7 termination impedance, and hybrid balance T7507 quad pcm codec with filters, pin information (continued) table 1. pin descriptions (continued) pin symbol type name/function 35 34 32 33 en 0 c en 1 c en 2 c en 3 c o enable. per-line data enable control for l8567 slic and l7583 solid-state switch. con- nect to en pin of l8567 slic and latch input of l7583 switch on a per-line basis. when low, data latch on l8567 and l7583 inputs are transparent and data will flow through the latch. when low, data is valid on l8567 supervision outputs. when high, data input latches on l8567 and l7583 are latched and data on l8567 supervision outputs is not valid. these pulses are generated internally by the T7507 and are generated sequentially when cclk is present. 40 do o data output for serial microprocessor interface. 41 di i data input for serial microprocessor interface. 42 cclk i control clock for serial microprocessor interface. this is the clock for the micro inter- face, slic, and switch parallel interface. this clock shifts serial information into the di pin during valid write-read cycles (defined by detection of valid csel ). this clock can be asynchronous to other system clocks. note: maximum clock frequency is 2.048 mhz. 43 csel i u chip select for serial microprocessor interface (active-low). chip select for serial microprocessor interface. an internal pull-up is on csel . 44 ifs i d inhibit frame separation. if this bit is set to 0, fsep functions as defined. if this bit is set to 1, the width of fsep has no effect on dx and d r timing relationship. in this case, timing is as if fsep = 1 mclk. an internal pull-down is on ifs. functional description pcm interface four channels of pcm data input and output are passed through two ports, d x and d r , so some type of time-slot assignment is necessary. the scheme used here is to utilize a timing mode of 32 time slots corre- sponding to a fixed master clock frequency of 2.048 mhz. transmit to pcm data is output on pin d x, and receive from pcm data is input on pin d r . time- slot assignment is done via the serial control data inter- face and is fully flexible. any channel of any codec may be assigned to any of the 32 time slots. see table 2 for additional details. delayed or nondelayed timing is selectable via the serial control data interface. in the nondelayed mode, time slot 0 nominally begins on the rising edge of fsep. in the delayed mode, time slot 0 nominally starts on the mclk positive edge following the negative edge that detects fsep. the start of pcm data can be delayed in 8 mclk increments by programming the time-slot bits via the microprocessor interface. there is a single frame sync separation input pin, fsep. this input provides two functions: it provides a clock for internal timing, and it sets the timing offset (if any) between the transmit and receive frames for a given channel on the pcm highway. there must always be an 8 khz signal on fsep, since this input provides the 8 khz clock required to maintain internal timing. by adjusting the duty cycle of fsep, the offset between the transmit and receive frames for a given channel on the pcm highway is set. the number of negative clock edges minus one that occurs while fsep is high is the delay (in clock periods) that is placed between the ris- ing edge of a transmit frame sign bit and the falling edge used by the receiver to sample the sign bit. if fsep is high for one clock period or less, the device makes the transmit edges and receive sampling edges one-half clock period apart. alternately, the inhibit frame separation (ifs) pin can be used to force the one-half clock period state, regard- less of the length of fsep. if the ifs pin is tied low, fsep functions as defined above in determining the pcm transmit/receive offset. if ifs is tied high, the width of fsep has no effect on the d x /d r timing rela- tionship; timing is as if fsep = 1 mclk. regardless of how ifs is tied, an 8 khz signal must still be applied to fsep to maintain internal timing. tying ifs high simply negates the effect of the duty cycle of fsep on the d x / d r timing relationship.
8 8 lucent technologies inc. data sheet august 1999 termination impedance, and hybrid balance T7507 quad pcm codec with filters, functional description (continued) pcm interface (continued) the entire device is placed in a powerdown mode if fsep remains low for 500 s. powerdown is not guar- anteed if mclk is lost unless the device is already in the powerdown mode due to fsep low for at least 500 s. the T7507 also offers an output pin, dxen . this pin is an open-drain output that pulses low during the period when the d x output is enabled. analog interface the analog input section (figure 3) includes an on-chip buffer op amp and internal gain. feedback paths (z t and hybal in figure 1) are included in the T7507 to generate signals needed for termination impedance and hybrid balance. when matched with a slic with a transconductance from tip/ring of 39.75 v/a and a differential gain to tip/ring of 2 (such as the lucent technologies l8567), and when a solid-state switch (such as the lucent l7583) and 50 w of series protection are used, the T7507 will synthesize a complex line termination impedance and hybrid balance network of 200 w + 680 w || 100 nf. additionally, the T7507 will fix the line circuit tip/ring to pcm transmit gain at 0 db (at 1000 hz, C0.7 db, +0.3 db) and will allow a user-select- able (via the serial control input) pcm to tip/ring receive gain of C3.5 db or C7.0 db (at 1000 hz, C0.7 db, +0.3 db). thus, the ac interface between the T7507 and the l8567 slic consists of a single dc blocking capacitor in the transmit direction, and a direct connec- tion requiring no external components in the receive direction. the T7507/l8567/l7583 chip set is designed to meet all mpt requirements for the peoples republic of china. transmission levels zero transmission-level points are specified relative to the digital milliwatt sequence prescribed by itu-t rec- ommendation g.711. under these conditions, an ana- log input of 0.0452 vrms applied to vf x in produces a 0 dbm digital code, while a 0 dbm code input at d r produces an output of 0.394 vrms differentially at vf r on/vf r op when using the C7.0 db gain mode (data bit d4 = 0). 5-4821(f) figure 3. typical analog input section microprocessor serial data control and l8567 slic/l7583 switch (or emr) control interfaces the basic logic control scheme is a serial data interface between the microcontroller and the T7507. through this interface, an 8-bit input control word and an 8-bit output status word is passed between the T7507 and microcontroller. the input control word contains infor- mation for the T7507, l8567 slic, and l7583 switch. the output status word contains off-hook and thermal shutdown status information from the l8567 slic and l7583 switch. see the input word definition and out- put word definition sections of this data sheet for spe- cific details on the input and output words. control and status information are passed between the T7507 and l8567 slic/l7583 switch via a latched par- allel data interface. data latches are integrated into the l8567 slic inputs and outputs and l7583 switch inputs. thus, a given data i/o on the T7507 serves the corresponding data i/o on the l8567 slic for the four channels associated with the quad T7507. additionally, a given data output on the T7507 serves the corre- sponding data inputs on the l7583 switch for the four channels associated with the quad T7507. status infor- mation from the l7583 switch is passed to the T7507 on a per-line basis. the T7507 control interface consists of an 8-bit input serial shift register, an 8-bit output serial shift register, an 8-bit loop status input latch, logic to generate the enable (en ) pulses required to control the slic and switch data latches, interface logic/buffers between the di shift register and the internal codec control, and interface logic buffers between the slic/switch output control leads. slic 26 db to codec filters T7507 c 1 3 0.07 m f vf x in r 3 100 k w v cm = 2.4 v
lucent technologies inc. 9 data sheet august 1999 termination impedance, and hybrid balance T7507 quad pcm codec with filters, functional description (continued) microprocessor serial data control and l8567 slic/l7583 switch (or emr) control interfaces (continued) the serial data interface has pins for data in (di), data out (do), chip select (csel ), and control clock (cclk). data is read by the microcontroller from the output shift register at the T7507 do lead. the T7507 reads data from the microcontroller into the data input shift register at the di lead. the loop status latch stores updated supervision information from the slic and switch until it is transferred to the do shift register. on the falling edge of csel , the first bit of do output data becomes valid and ready for transmission in the time specified by tcslccl. on the next falling cclk edge, the microprocessor will read the first bit of valid data from the T7507 do output. also, on this first falling cclk edge, the T7507 will read the first bit of control information on the di input from the microcontroller. thus, upon the falling csel edge, the microcontroller must have valid data ready at its data out lead in a time specified by tcivccl. on the next seven falling cclk edges, the remaining seven status bits are read by the microcontroller at the T7507 do lead and the remaining 7 control input bits are read by the T7507 at the di lead from the micro- controller. during the time tcclcsh, which is the period after the eight falling cclk edges, the data at the di register is applied to the T7507 codec and made available to the l8567 slic and l7583 switch input data latches. data is applied only if csel is low and has remained low on the eighth negative edge of cclk. upon the falling edge of csel , do data is passed from the loop status latch to the do shift register. during the period when csel is low, do status data will not be passed from the loop status latch to the do shift regis- ter. consecutive read/write periods are not allowed. csel must remain high for a specified time, tcshcsl, before csel can transition low again. during csel low interval, the T7507 generates an en pulse low for one of the four channels served by the particular T7507. these en pulses are generated sequentially. thus, if en 0 is generated on a given csel low, en 1 will be generated during the next csel low, etc. only one of the four en outputs associated with a given T7507 codec will be low during a given csel interval. enable transfers when cclk is bursted with csel when en is low, status information from the slic and switch is updated in the T7507 8-bit loop status latch. this data will be transferred into the data out shift regis- ter and shifted out to the microcontroller on the next csel cycle. thus, to make a write from the l8567 slic or l7583 switch, it takes two csel cycles: the first to create an en pulse for a given channel and to shift updated status information to the 8-bit status latch, and the second csel cycle to shift the updated chan- nel information to the microcontroller. each time the csel goes low and status information is shifted to the microcontroller, only one of the four channels has new status data; the other channels are shifting out status data that has previously been presented to the micro- controller. thus, it takes five csel cycles to a T7507 device to ensure that supervision data for each of the four channels associated with the T7507 device has been updated. when en goes low, updated control information is also fed to the slic and switch from the T7507. since en for each channel is generated sequentially during suc- cessive csel , four csel s to a given T7507 device are required to ensure that updated control information is given to each of the four channels. note that to apply ringing, before the ring relay is acti- vated to apply power ringing to the subscriber loop, the l8567 slic must first be changed from the low-power scan mode to the active mode. this is because the ring trip detector is not active when the l8567 slic is in the low-power scan mode. thus, application of ringing to a given channel may require as many as eight csel cycles to the T7507 associated with the channel. enable transfers when cclk is not restricted to csel low the T7507 will continue to generate en pulses sequentially, free-running with cclk falling edges, when csel is not applied low. thus, if there are long periods of time when csel low is not presented to a given T7507 device, enable pulse low will be generated sequentially during this time. this feature allows for the most recent slic and switch status information to be maintained in the 8-bit loop status latch during long periods of time when csel to a given T7507 device is maintained high.
10 10 lucent technologies inc. data sheet august 1999 termination impedance, and hybrid balance T7507 quad pcm codec with filters, functional description (continued) enable transfers when cclk is not restricted to csel low (continued) if csel drops low, during the time an en for a given channel is low, the write cycle to/from the codec will be aborted. however, the en pulse that will be generated during the eight cclk cycles that csel is low will be for the channel whose en pulse was aborted by the csel dropping low. thus, for example, if en 2 is low and during the time en 2 is low csel is also low, en 2 will immediately go high and any associated write is aborted. then the en that is generated because csel is low is for channel 2. the T7507 generates the required enable control sig- nals for the l8567 input data latches, the output data latches, and the l7583 input data latch. a logic low on the l8567 or l7583 latch enable input allows data to flow through the latch. a logic high on the latch enable of the l8567 or l7583 latches the latch. the latch enable is output on a per-line basis from the en 0c, en 1c, en 2c, and en 3c outputs of the T7507. the l8567 slic and l7583 latches are level sensitive, so when en x is low, the data from the slic and switch latch flows directly to the T7507 loop status latch. after a high-to-low csel transition, on the next falling edge of cclk, data is transferred from the loop status latch to the serial shift register. therefore, it is not desirable to update the loop status register on this cclk edge. for this reason, en pulses are generated during the rising edge of cclk. note that loop status information from the four chan- nels is accepted on a multiplexed basis at the nstatc input of the T7507. this information is decoded by the T7507 and placed at the appropriate bit in the 8-bit out- put word. nstat is a wired-or of the loop closure and ring trip status from the l8567 slic. thermal shutdown information from the four slics is accepted on a multiplexed basis at the ntsdc input of the T7507. thermal shutdown information from the l7583 switch is accepted on a per-line basis from the four l7583s associated with the quad T7507. the ther- mal shutdown information from the slics is decoded by the T7507 and then anded with the thermal shut- down information from the corresponding l7583. this thermal shutdown information for the slic and switch is then placed at the appropriate bit in the 8-bit output word. the control word contains control information for the T7507, l8567 slic, and l7583 switch. thus, the con- trol bits for the l8567 slic and l7583 switch need to be transferred via the latched parallel control interface. slic control information for the four channels is trans- ferred on a multiplexed basis through the b0c and b1c output leads on the T7507. l7583 control information (or l8567 relay driver information) is transferred on a multiplexed basis through the rd1c, rd2c, and rd3c output leads. three features for the T7507 can be programmed via the serial data interface. the channel receive gain and codec powerup or powerdown are set on a per-channel basis. delayed and nondelayed timing mode is set glo- bally; all four channels are set to the same mode via the serial data bus. additionally, pcm time-slot assign- ment is set via the serial data input bus. the l8567 b0, b1 state control inputs are latched data inputs. control data is sent to these inputs via the b0c and b1c outputs of the T7507. the b0c and b1c out- puts of the T7507 are meant to control the four slics associated with the quad T7507. switch control information is sent to the in ring , in testin , or in testin logic control inputs of the l7583 switch, or to the rd1i, rd2i, and rd3i relay driver con- trol inputs of the l8567 slic (if emrs are used) via the rd1c, rd2c, and rd3c T7507 parallel data control outputs. again, the l7583 state control inputs and the l8567 relay driver control inputs are latched, so control information from the rd1c, rd2c, and rd3c T7507 control outputs are meant to control four lines. the l8567 slic outputs loop status information via the latched nstat output. nstat is a wired-or or the out- puts of the l8567 slics loop closure detector and ring trip detector. the loop status information is input to the T7507 via the nstatc input. since the l8567 slic nstat bit is latched, the slic output from the four channels associated with the T7507 are accepted at nstatc. the l8567 slic also outputs a thermal shutdown flag via the latched ntsd output. this thermal shutdown information is input to the T7507 via the ntsdc input. since the l8567 slic nstat and ntsd bits are latched, the slic output from the four channels associ- ated with the T7507 are accepted at nstatc and ntsd, respectively. the l7583 also outputs thermal shutdown status via the tsd output. the tsd output on the l7583 is not latched, so the tsd information is input to the T7507 for the four channels associated with the quad T7507 on a per-line basis via the ntsd0, ntsd1, ntsd2, and ntsd3 T7507 inputs. the multiplexed thermal shutdown information from the four l8567 slics and the per-line thermal shutdown information from the four l7583 switches are manipu- lated by the T7507 into a per-channel thermal shut- down bit and output on the serial data output do pin.
lucent technologies inc. 11 data sheet august 1999 termination impedance, and hybrid balance T7507 quad pcm codec with filters, functional description (continued) enable transfers when cclk is not restricted to csel low (continued) it is recommended that a polling process be used during idle periods to ensure that a loop closure detection is rec- ognized by the microcontroller. the maximum nominal control clock (cclk) frequency is 2.048 mhz. also note that do is 3-stated based on the state of csel . this allows multiple do outputs from multiple T7507s to be tied to a common do bus. table 2. microprocessor interface descriptions symbol description cclk may be gapped; maximum frequency is 2.048 mhz. en pulses are generated on rising cclk edges. csel a low-going csel initiates a write to the T7507 via the di pin. at the same time, this initiates a read from the T7507 on the do pin. data is written and read on the first eight cclk negative transitions after csel goes low. data is applied to the T7507 operation only if csel is low on the eighth nega- tive edge of cclk. consecutive writes are not allowed; csel must go high for a minimum 50 ns between write cycles. additionally, data is shifted from the loop status latch to the serial shift register on the first falling cclk pulse after csel goes low. di pin for serial input data. input data is an 8-bit word which sends control information from the micro- controller to the T7507, l8567 slic, and l7583 switch. T7507 information is codec state information and pcm time-slot assignment. l8567 and l7583 control information is passed to these components via parallel control output pins. see input word definition section for additional details. do pin for serial data output. output data is an 8-bit word which sends status information from T7507 par- allel status inputs to the microcontroller via the serial data interface. status information is received from the T7507 via the parallel control inputs from the l8567 slic and l7583 switch. see output word definition section for additional details.
12 lucent technologies inc. data sheet august 1999 termination impedance, and hybrid balance T7507 quad pcm codec with filters, functional description (continued) input word definition the control data input on di is an 8-bit word of the format: c1 c0 m d4 d3 d2 d1 d0 bits c0 and c1 are the channel select bits. bit m is a mode control bit. bits d0, d1, d2, and d3 are data bits. bit d4 can be either a mode control bit or a data bit. if m is set to 0, the data word is set to the pcm time-slot assignment mode and bit d4 is a data bit. if m is set to 1, then d4 is also a mode set bit. if m, d4 = 1, 0, then the data word rep- resents the relay/switch control delayed/nondelayed timing mode. if m, d4 = 1, 1 then the data word represents the codec/slic control mode. * delayed/nondelayed pcm timing is a global parameterall channels are programmed to the most recent value. to program pcm timin g, use c0 = c1 = 0. (that is channel 0.) m = 1, d4 = 0. when programming c1, c0 = 01, m = 1, d4 = 0, then d3 must be programmed to 0. when c1, c0 = 10, 11, m = 1, d4 = 0, then d3 is ignored. note: do not assign two channels to the same time slot. if two channels are assigned to the same time slot, the result is indete rminate. it is rec- ommended that time-slot assignment should only be done when the channel is powered down. if multiple chips are tied to the same d x bus, this can result in bus contention. thus, reassignment of time slots should be done before the channel is powered up. for a ll codecs, upon powerup, channel 0 will be assigned to time slot 0, channel 1 will be assigned to time slot 1, channel 2 will be assigned to time slot 2, and channel 3 will be assigned to time slot 3. table 3. c0, c1 channel select c1 c0 channel 00 0 01 1 10 2 11 3 table 4. m, d4, d3, d2, d1, d0 mode select and data md4d3d2d1d0 0 time-slot assignment time-slot assignment time-slot assignment time-slot assignment time-slot assignment 1 0 delayed/nondelayed pcm timing mode or reserved* relay state control information 3 relay state control information 2 relay state control information 1 1 1 T7507 per channel powerup/powerdown channel receive gain b1 slic control bit b0 slic control bit table 5. m = 0 mode (pcm time-slot assignment) d4 d3 d2 d1 d0 function 00000time slot 0 00001time slot 1 . . . 11111time slot 31
lucent technologies inc. 13 data sheet august 1999 termination impedance, and hybrid balance T7507 quad pcm codec with filters, functional description (continued) input word definition (continued) table 6. m = 1, d4 = 0 mode (relay state control and delayed/nondelayed timing) * delayed or nondelayed timing is a global parameter. all channels will use the most recently programmed value. note: upon powerup, d3 = d2 = d1 = d0 = 0; that is, delayed timing mode and all relay drivers in the not active state, or 0, 0, 0, are applied to l7583 solid-state relay, which is the idle/talk state. table 7. m = 1, d4 = 1 mode (codec state control and slic state control) * receive gain of C3.5 and C7.0 will be achieved in a 200 w + 680 w || 0.1 f termination, when using the T7507 with the l8567 slic, l7583 switch, and 50 w protection resistors. d3 d2 d1 d0 function 0 x x x delayed timing mode (see figure 12)*. with c0 = c1 = 00, bit d3 set pcm delayed or non- delayed timing. with c0, c1 = 01, 10, 11, bit d3 is ignored. 1 x x x nondelayed timing mode (see figure 13)*. with c0 = c1 = 00, bit d3 set pcm delayed or nondelayed timing. with c0, c1 = 01, 10, 11, bit d3 is ignored. x 0 x x T7507 driver output rd3c at logic low. if T7507 driver output rd3c is applied to the l8567 slic rd3i input, this will place the relay driver output on the l8567, rd3o, into the relay not active state. if T7507 output rd3c is used to drive the logic inputs of an l7583 solid- state switch, a logic 0 is applied. x 1 x x T7507 driver output rd3c at logic high. if T7507 driver output rd3c is applied to the l8567 slic rd3i input, this will place the relay driver output on the l8567, rd3o, into the relay active state. if T7507 output rd3c is used to drive the logic inputs of an l7583 solid-state switch, a logic 1 is applied. x x 0 x T7507 driver output rd2c at logic low. if T7507 driver output rd2c is applied to the l8567 slic rd3i input, this will place the relay driver output on the l8567, rd2o, into the relay not active state. if T7507 output rd2c is used to drive the logic inputs of an l7583 solid- state switch, a logic 0 is applied. x x 1 x T7507 driver output rd2c at logic high. if T7507 driver output rd2c is applied to the l8567 slic rd3i input, this will place the relay driver output on the l8567, rd2o, into the relay active state. if T7507 output rd2c is used to drive the logic inputs of an l7583 solid-state switch, a logic 1 is applied. x x x 0 T7507 driver output rd1c at logic low. if T7507 driver output rd1c is applied to the l8567 slic rd3i input, this will place the relay driver output on the l8567, rd1o, into the relay not active state. if T7507 output rd1c is used to drive the logic inputs of an l7583 solid- state switch, a logic 0 is applied. x x x 1 T7507 driver output rd1c at logic high. if T7507 driver output rd1c is applied to the l8567 slic rd3i input, this will place the relay driver output on the l8567, rd1o, into the relay active state. if T7507 output rd1c is used to drive the logic inputs of an l7583 solid-state switch, a logic 1 is applied. d3 d2 d1 d0 function 0 x x x T7507 channel standby 1 x x x T7507 channel powerup x 0 x x channel receive gain C3.5 db* x 1 x x channel receive gain C7.0 db* x x 1 1 l8567 slic powerup, forward battery x x 0 1 l8567 slic powerup, reverse battery x x 1 0 l8567 slic low-power scan x x 0 0 l8567 disconnect
14 14 lucent technologies inc. data sheet august 1999 termination impedance, and hybrid balance T7507 quad pcm codec with filters, functional description (continued) output word definition the status data input on d0 is an 8-bit word of the for- mat: nstat-ch0, ntsd-ch0, nstat-ch1, ntsd-ch1, nstat-ch2, ntsd-ch2, nstat-ch3, ntsd-ch3 where: nstat-ch[0:3] is the wired-or loop supervision status of the off-hook detector and ring trip detector from channel [0:3]. ntsd-ch[0:3] is the wire-ored thermal shutdown status of the l8567 slic and l7583 for channel [0:3]. powerup this section defines the state of the T7507 when power is first applied to the device. T7507 upon initial application of power, the T7507 is in the full-chip powerdown state and delayed timing mode. output word with the initial csel , after application of power, all eight bits of the output word are undefined. with subse- quent csel , all eight bits of the output word will be set to zero. the output word will remain all 0s until applica- tion of en pulses to update the output status informa- tion. an output word of all 0s implies that all four channels are in thermal shutdown state and are off- hook. en status upon application of power, all four en channels will be at logic 1 (which means that no control data is trans- ferred to, and no status information is received from, the slic or switch). all en will remain at logic 1 until application of an initial fsep pulse, at which time en is created as defined in the microprocessor interface sec- tion of this data sheet. input wordpcm interface upon application of power, the pcm time-slot assign- ment defaults to the following time-slot assignment: ch0 time slot 0 ch1 time slot 1 ch2 time slot 2 ch3 time slot 3 input wordrelay control/timing upon application of power, all relay driver control inputs are forced to logic 0. if the relay driver outputs are tied to the l8567 relay driver inputs, upon application of an en signal, the relay drivers are forced into the off state. if applied to the l7583 control input, upon application of an en pulse, the l7583b is forced into the idle/talk state. input wordcontrol mode upon application of power, the receive gain is C3.5 db and with the b0/b1 control outputs set to 0/0. note that b0/b1 = 0/0, the l8567 slic is set into the disconnect state upon application of en pulse. state definitions powerup all circuits are active. all channels are ready for trans- mission. en pulses are generated free-running with cclk. standby this mode is programmed on a per-channel basis via the microprocessor control interface. in this mode, indi- vidual channels are powered down (not ready for trans- mission). all reference circuits are always powered up. en pulses are generated free-running with cclk. ana- log outputs are held at a nominal 2.35 v. full-chip powerdown this is a global parameter; that is, all channels are glo- bally set into this mode. in this mode, all channels and all reference circuits are powered down. en is forced to logic high. the T7507 is in this state upon application of power. the T7507 enters this state if fsep is removed for four 8 khz frames. the T7507 will remain in this state until reapplication of fsep.
lucent technologies inc. 15 data sheet august 1999 termination impedance, and hybrid balance T7507 quad pcm codec with filters, absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are absolute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. handling precautions although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo- sure to electrostatic discharge (esd) during handling and mounting. lucent employs a human-body model (hbm) and a charged-device model (cdm) for esd-susceptibility testing and protection design evaluation. esd voltage thresholds are dependent on the circuit parameters used to define the model. no industry-wide standard has been adopted for cdm. however, a standard hbm (resistance = 1500 w , capacitance = 100 pf) is widely used and therefore can be used for comparison purposes. the hbm esd threshold presented here was obtained by using these circuit parameters: electrical characteristics specifications apply for t a = C40 c to +85 c, v dd = 5 v 5%, mclk = 2.048 mhz, and gnd = 0 v, unless other- wise noted. dc characteristics table 8. digital interface parameter symbol min max unit storage temperature range t stg C55 150 c power supply voltage v dd 6.5 v voltage on any pin with respect to ground C0.5 0.5 + v dd v maximum power dissipation (package limit) p d 600 mw hbm esd threshold voltage device rating T7507 >2000 v parameter symbol test conditions min typ max unit input low voltage v il all digital inputs 0.8 v input high voltage v ih all digital inputs 2.0 v input current i i any digital input gnd < v in < v dd C10 10 a input current, pins with pull-up ( csel ) i i any digital input gnd < v in < v dd 2 150 a input current, pins with pull-down (fsep, ifs) i i any digital input gnd < v in < v dd C2 C150 a output low voltage v ol dxen , d x = 3.2 ma 0.4 v output high voltage v oh d x = C3.2 ma 2.4 v d x = C320 a 3.5 v output current in high-impedance state i oz dxen , d x C30 30 a input capacitance c i 5 pf
16 lucent technologies inc. data sheet august 1999 termination impedance, and hybrid balance T7507 quad pcm codec with filters, electrical characteristics (continued) dc characteristics (continued) table 9. power dissipation power measurements are made with outputs unloaded. * a nominal 6 ma decrease in current per channel put into standby. transmission characteristics table 10. analog interface parameter symbol test conditions min typ max unit powerdown current i ddo mclk present; fsep = 0.4 v 0.4 1 ma powerup current* i dd1 mclk, fsep present; all channels powered up 33 40 ma standby current i dds mclk, fsep present; all channels powered down 7 10 ma parameter symbol test conditions min typ max unit input resistance, vf x in r vf x i 1 v < |vfxi| < 4 v 100 300 k w input voltage, vf x in v ix relative to ground 2.25 2.35 2.5 v load resistance, vf r on to vf r op rl vf r o differential load 2 k w load capacitance, vf r on to vf r op cl vf r o 100 pf output resistance, vf r o ro vf r o 0 dbm0, 1020 hz pcm code applied to d r 2 20 w channel under test in powerdown 3000 10000 w dc output voltage, vf r op, vf r on v or alternating 0 a-law pcm code applied to d r 2.20 2.35 2.5 v dc output voltage, vf r op, vf r on standby vo rpd fsep = active, no load, channel under test in powerdown 2.15 2.35 2.65 v differential dc output vf r op C vf r on d v or alternating 0 a-law pcm code applied to d r C60 60 mv output leakage current, vf r op, vf r on powerdown io vf r o fsep = 0.4 v C30 30 a output voltage swing, vf r op C vf r on v swr rl = 2 k w (differential) 2.6 vp-p
lucent technologies inc. 17 data sheet august 1999 termination impedance, and hybrid balance T7507 quad pcm codec with filters, transmission characteristics (continued) ac transmission characteristics unless otherwise noted, the analog input is a C26 dbm (at 813 w ), 1020 hz sine wave. the digital input is a pcm bit stream equivalent to that obtained by passing a 0 dbm0, 1020 hz sine wave through an ideal encoder. the out- put level is sin(x)/x-corrected. table 11. absolute gain * combination test results are translated into system-level characteristics guaranteed by table 21, figure 8, and figure 9. ? overall system-level tolerances are +0.3 db to C0.7 db in both directions. therefore, nominal analog levels are shifted by C0.2 db. parameter ? symbol ? test conditions ? min * ? typ ? max * ? unit ? encoder milliwatt response (transmit gain tolerance) emw signal input of 0.0452 vrms (C26 dbm at 813 w at 1020 hz) C0.20 dbm0 decoder milliwatt response (receive gain tolerance) dmw measured differential relative to 0.902 vrms, pcm input of 0 dbm0 1020 hz rl = 10 k w , receive gain in C7.0 db mode C7.20 dbm0 relative gain variation referenced to dmw rgr decoder gain = C3.5 db mode 3.5 db table 12. gain tracking parameter symbol test conditions min typ max unit transmit gain tracking error sinusoidal input a-law gt x +3 dbm0 to C37 dbm0 C37 dbm0 to C50 dbm0 C0.25 C0.50 0.25 0.50 db db receive gain tracking error sinusoidal input a-law gt r +3 dbm0 to C37 dbm0 C37 dbm0 to C50 dbm0 C0.25 C0.50 0.25 0.50 db db table 13. distortion parameter symbol test conditions min typ max unit transmit signal to distortion sd x 3 dbm0 3 vf x i 3 C30 dbm0 35 db C30 dbm0 3 vf x i 3 C40 dbm0 29 db C40 dbm0 3 vfxi 3 C45 dbm0 25 db receive signal to distortion sd r 3 dbm0 3 vf r o 3 C30 dbm0 35 db C30 dbm0 3 vf r o 3 C40 dbm0 29 db C40 dbm0 3 vf r o 3 C45 dbm0 25 db single-frequency distortion, transmit sfd x 200 hz3400 hz, 0 dbm0 input, output any other single frequency 3400 hz C38 dbm0 single-frequency distortion, receive sfd r 200 hz3400 hz, 0 dbm0 input, output any other single frequency 3400 hz C40 dbm0 intermodulation distortion imd transmit or receive, two frequencies in the range (300 hz3400 hz) at C6 dbm0 C42 dbm0
18 lucent technologies inc. data sheet august 1999 termination impedance, and hybrid balance T7507 quad pcm codec with filters, transmission characteristics (continued) ac transmission characteristics (continued) table 14. envelope delay distortion * varies as a function of time slots chosen. overload compression figure 4 shows the region of operation for encoder signal levels above the reference input power (0 dbm0). 5-3586(f) figure 4. overload compression parameter symbol test conditions min typ max unit t x delay, absolute* d xa f = 1600 hz 165 to 425 s t x delay, relative to 1600 hz d xr f = 500 hz600 hz f = 600 hz800 hz f = 800 hz1000 hz f = 1000 hz1600 hz f = 1600 hz2600 hz f = 2600 hz2800 hz f = 2800 hz3000 hz 220 145 75 40 75 105 155 s s s s s s s r x delay, absolute* d ra f = 1600 hz 135 135 to 395 s r x delay, relative to 1600 hz d rr f = 500 hz1000 hz f = 1000 hz1600 hz f = 1600 hz2600 hz f = 2600 hz2800 hz f = 2800 hz3000 hz C44 C30 90 125 175 s s s s s round trip delay, absolute* d rta any time slot/channel to any time slot/channel f = 1600 hz 305 to 625 s 1 2 3 4 5 6 7 8 9 123456789 acceptable region fundamental input power (dbm) fundamental output power (dbm)
lucent technologies inc. 19 data sheet august 1999 termination impedance, and hybrid balance T7507 quad pcm codec with filters, transmission characteristics (continued) ac transmission characteristics (continued) table 15. decoder limits relative to gain at 1020 hz table 16. encoder limits, includes effect of termination impedance filter relative to gain at 1020 hz table 17. termination impedance limits relative to gain at 1020 hz table 18. hybrid path limits relative to gain at 1020 hz frequency (hz) min typ max unit 15.6 C0.150 0.150 db 46.8 C0.150 0.150 db 62.5 C0.150 0.150 db 453 C0.150 0.150 db 2734 C0.150 0.150 db 3140 C0.550 0.150 db 3375 C0.850 0.150 db 3984 C13.40 db 5015 C28.00 db frequency (hz) min typ max unit 15.6 C30.500 db 46.8 C25.600 db 62.5 C29.400 db 453 0.400 0.700 db 2734 C2.950 C2.650 db 3140 C3.950 C3.250 db 3375 C4.550 C3.850 db 3984 C18.30 db 5015 C35.00 db frequency (hz) min typ max unit 46.8 0 1 db 62.5 0.3 0.8 db 453 0.45 0.65 db 2734 C2.95 C2.65 db 3140 C3.60 C3.20 db 3375 C4.05 C3.55 db 3984 C5.05 C4.45 db 5015 C6.35 C5.65 db frequency (hz) min typ max unit 46.8 C26.000 db 62.5 C30.000 db 453 C0.180 0.180 db 2734 C0.410 C0.050 db 3140 C0.700 0.100 db 3375 C1.640 C0.840 db 3984 C25.00 db
20 lucent technologies inc. data sheet august 1999 termination impedance, and hybrid balance T7507 quad pcm codec with filters, transmission characteristics (continued) ac transmission characteristics (continued) table 19. noise table 20. interchannel crosstalk (between channels) note: for interchannel, crosstalk into the transmit channels (vfxin) can be significantly affected by parasitic capacitive feeds from vf r o out- puts. pwb layouts should be arranged to keep these parasitics low. the equivalent resistor looking from vfxin toward vitr (figu re 16) should be kept as low as possible to minimize crosstalk. a maximum of 7 k w at 3 khz is recommended. this is easily achievable in this design with the structure as shown in figure 16. parameter symbol test conditions min typ max unit transmit noise n xp C68 dbm0p receive noise n rp pcm code is a-law positive one C75 dbm0p noise, single frequency f = 0 khz100 khz n rs vf x in = 0 vrms, measurement at vf r o, d r = d x C53 dbm0 power supply rejection transmit psr x v dd = 5.0 vdc + 100 mvrms: f = 0 khz4 khz f = 4 khz50 khz 36 30 db db power supply rejection receive psr x pcm code is positive one lsb. v dd = 5.0 vdc + 100 mvrms: f = 0 khz4 khz f = 4 khz25 khz f = 25 khz50 khz 36 40 30 db db db spurious out-of-band signals at vf r o relative to input sos 0 dbm0, 300 hz3400 hz input pcm code applied: 4600 hz7600 hz 7600 hz8400 hz 8400 hz50 khz C30 C40 C30 db db db parameter symbol test conditions min typ max unit transmit to receive crosstalk 0 dbm0 transmit levels ct xx-ry f = 300 hz3400 hz idle pcm code for channel under test; 0 dbm0 into any other single-channel vf x in C90 C75 db receive to transmit crosstalk 0 dbm0 receive levels ct rx-xy f = 300 hz3400 hz vf x in = 0 vrms for channel under test; 0 dbm0 code level on any other single-channel d r C90 C75 db transmit to trans- mit crosstalk 0 dbm0 transmit levels ct xx-xy f = 300 hz3400 hz 0 dbm0 applied to any single-channel vf x in except channel under test, which has vf x in = 0 vrms C90 C75 db receive to receive crosstalk 0 dbm0 receive levels ct rx-ry f = 300 hz3400 hz 0 dbm0 code level on any single-channel d r except channel under test, which has idle code applied C90 C75 db
luce n t techn o l o gi e s i nc. 21 data sheet a ugust 1999 t ermination impedanc e , and hybrid balance T7507 quad pcm codec with filte r s, chip set p er f ormance specifications w h en u sing th e t750 7 , l 8 567 s l i c , l 75 8 3 s o lid-s t ate s witch, a nd 5 0 w p r o tecti o n resistor s , the f oll o win g lin e card r e quirem e nts ar e achi e v e d ; speci f ied te r m i n ation imp e da n ce is sh o w n i n fig u re 5. 5 -53 2 4a( f ) figure 5. t ermination impedance g a in g a in fl a tnes s in b a nd ga i n f l atnessou t o f bandhigh frequenc i es th e t r a nsmit and recei v e directi o ns fre q ue n cy-de p en- de n t loss relati v e to g a in at 3 400 hz is sh o wn b el o w . this sp e cifica t ion is m e t b y u sing t he t 7 50 7 , l8 5 67 s l i c , l 75 8 3 solid-state s witch , and 5 0 w protection res i stors ( 200 w + 6 80 w || 0 . 1 f t e r mina t io n ). 5 -53 4 0( f ) figur e 6 . t ransmit and receive direction frequency-dependent loss relative to gain at 3 400 hz the loss f o r fre q ue n cies 3 400 hz < f < 4 6 00 hz is g i v en b y : b = 1 2 .5 t able 21. g a in gain @ 10 2 0 hz m i n t yp max unit t ra n s m it C0.7 0 0.3 db r ecei v e C4.2 C3.5 C3.2 db r ecei v e C7.7 C7.0 C6.7 db t abl e 22 . g a in flatnes s in b a nd the in-b a nd f r e que n cy-de p en d en t loss rel a ti v e to gain a t freq u ency = 10 2 0 hz, f o r th e t r a nsmit and rec e i v e dir e c t io n s . this s p ecific a ti o n is m et b y using the t75 0 7, l 8 567 s l i c , l 75 8 3 solid-state s witch , and 5 0 w protectio n r e sis t ors (2 0 0 w + 6 8 0 w || 0.1 f te r m i n ation). frequency (hz) m i n max unit 30 0 400 C0.3 1.00 db 40 0 600 C0.3 0.75 db 6 00 24 0 0 C0.3 0.35 db 2 40 0 30 0 0 C0.3 0.55 db 3 00 0 34 0 0 C0.3 1.50 db 68 0 w 0.1 m f 200 w 0 C5 10 12.5 20 25 30 lo ss (db ) 3400 4000 4600 5000 acc e pt a ble regi o n fre q u e ncy ( hz) 1 p 4 000 f C () 1 200 ---- - ------ - ------- - ------ - - - s i n C db
22 22 lucent technologies inc. data sheet august 1999 termination impedance, and hybrid balance T7507 quad pcm codec with filters, chip set performance specifications (continued) gain flatnessout of bandlow frequencies transmit direction only, loss relative to 1020 hz. this specification is met by using the T7507, l8567 slic, l7583 solid-state switch, and 50 w protection resistors (200 w + 680 w || 0.1 f termination). table 23. gain flatnessout of bandlow frequencies loss vs. level relative to loss at C10 dbm input at 1020 hz this specification is met by using the T7507, l8567 slic, l7583 solid-state switch, and 50 w protection resistors (200 w + 680 w || 0.1 f termination). 5-5341(f) figure 7. loss vs. level return loss the following template is achieved. 5-5325(f) figure 8. return loss hybrid balance the following template is achieved. 5-5326(f) figure 9. hybrid balance frequency (hz) min loss (db) 16.67 30 40 26 50 30 60 30 +3 dbm0 C10 C40 C50 C55 1.6 0.6 0.3 0 C0.3 C0.6 C1.6 loss (db) 18 rl (db) 14 300 500 2000 3400 frequency (hz) 20 tbrl (db) 16 300 500 2500 3400 frequency (hz)
lucent technologies inc. 23 data sheet august 1999 termination impedance, and hybrid balance T7507 quad pcm codec with filters, microprocessor interface table 24. T7507 microprocessor interface timing frequency of cclk = 2.048 mhz. symbol parameter test conditions min max unit tcclcch time of cclk low 160 ns tcchccl time of cclk high 160 ns tcchcch period of cclk 488 ns tcch1cch2 rise time of cclk 50 ns tccl1ccl2 fall time of cclk 50 ns tcslccl csel low to cclk transition measured from first cclk low transition 50 ns tcclcsh cclk low to csel high measured from eighth cclk low transition 30 ns tcivccl setup time, data input/output valid to cclk low 50 ns tcclcix hold time, cclk low to data input/output invalid 50 ns tcshcsl minimum time between writes 50 ns tsu1bo2 setup time for b0b1 data 488 ns tsu2bo1 setup time for b0b1 data 488 ns tsu1rd setup time for rd1, rd2, rd3 data 488 ns tsu2rd setup time for rd1, rd2, rd3 data 488 ns tenl enable pulse width 977 ns
24 lucent technologies inc. data sheet august 1999 termination impedance, and hybrid balance T7507 quad pcm codec with filters, microprocessor interface (continued) 5-5808(f) figure 10. slic/switch interface timing 5-4517.b(f) figure 11. microprocessor interface write timing 1465 ns at cclk cclk en nstat/ntsd tsu1bo2 tccl1ccl2 rd1, rd2, rd3 csel b0/b1 tenl tcch1cch2 2.048 mhz tsu1rd tsu2bo1 tsu2rd tcchcch tcshcsl tcclcsh tccl1ccl2 tcchccl tcclcch tcch1cch2 tcclcix tcclcix tcslccl tcivccl tcivccl d0 d1 c1 d2 d3 d4 m d0 m nstat ch0 ntsd ch0 nstat ch1 ntsd ch1 nstat ch2 ntsd ch2 ntsd ch3 nstat ch3 nstat ch0 cclk csel di do
lucent technologies inc. 25 data sheet august 1999 termination impedance, and hybrid balance T7507 quad pcm codec with filters, timing characteristics table 25. clock section see figures 1214. table 26. T7507 transmit section (delayed timing) see figure 12. * timing parameter tmcldz is referenced to a high-impedance state. table 27. T7507 transmit section (nondelayed timing) see figure 13. * timing parameter tmchdz is referenced to a high-impedance state. table 28. T7507 receive section see figures 1214. symbol parameter test conditions min typ max unit tmchmcl1 clock pulse width 97 ns tcdc duty cycle, mc 40 60 % tmch1mch2 tmcl2mcl1 clock rise and fall time 0 15 ns symbol parameter test conditions min typ max unit tmchdv data enabled on ts entry 0 < c load < 100 pf 0 60 ns tmchdv1 data delay from mc 0 < c load < 100 pf 0 60 ns tmcldz* data float on ts exit c load = 0 15 100 ns tsphmcl frame-sync hold time 50 ns tmclsph frame-sync high setup 50 ns tsplmcl frame-sync low setup 50 ns tsphspl frame-sync pulse width 0.1 125 C tmchmch s symbol parameter test conditions min typ max unit tsphdv data enabled on ts entry 0 < c load < 100 pf 0 80 ns tmchdv1 data delay from fs x 0 < c load < 100 pf 0 60 ns tmchdz* data float on ts exit c load = 0 0 30 ns tsphmcl frame-sync hold time 50 ns tmclsph frame-sync high setup 50 ns tsplmcl frame-sync low setup 50 ns tsphspl frame-sync pulse width 0.1 125 C tmchmch s symbol parameter test conditions min typ max unit tdvmcl receive data setup 30 ns tmcldv receive data hold 15 ns tsphmcl frame separation hold time 50 ns tsplmcl frame separation low setup 50 ns
26 lucent technologies inc. data sheet august 1999 termination impedance, and hybrid balance T7507 quad pcm codec with filters, timing characteristics (continued) 5-3581.g(f) figure 12. T7507 transmit and receive timing, fsep = 1 mclk or ifs = 1, delayed timing (d0 = 0) 5-3581.h(f) figure 13. T7507 transmit and receive timing, fsep = 1 mclk or ifs = 1, nondelayed timing (d0 = 1) tmchmcl1 tsphmcl tmch1mch2 tmcl2mcl1 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 1 bit 2 bit 3 bit 5 bit 4 bit 6 bit 7 bit 8 123456781 mclk fsep dx time slot tsplmcl tsplmcl tmchdv1 tmcldz d r tdvmcl tmcldv d r stable tmchdv1 tsphspl tmclsph tsphmcl tmch1mch2 tmcl2mcl1 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 1 bit 2 bit 3 bit 5 bit 4 bit 6 bit 7 bit 8 123456781 mclk fsep dx time slot tsplmcl tsplmcl tmchdv1 tmchdz d r tdvmcl tmcldv d r stable tmchdv1 tsphspl tmclsph tmchmcl1
lucent technologies inc. 27 data sheet august 1999 termination impedance, and hybrid balance T7507 quad pcm codec with filters, timing characteristics (continued) 5-3582.b(f) figure 14. T7507 receive timing, fsep > 1 mclk and ifs = 0, delayed timing (d3 = 0) 5-4853(f) figure 15. typical frame sync timing (ifs = 0) programming: 00010111 channel 0 in time slot 23 00100101 channel 1 in time slot 5 01001111 channel 2 in time slot 15 01101000 channel 3 in time slot 8 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 12345678 mclk fsep d r tdvmcl tmcldv d r stable time slot tmchmcl1 tsplmcl tsphmcl 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 x0 r2 r0 x1 x3 r1 r3 x2 fsep d x d r time slots
28 lucent technologies inc. data sheet august 1999 termination impedance, and hybrid balance T7507 quad pcm codec with filters, applications 5-5807a(f) figure 16. basic loop start application using the T7507 and the l7583 switch for 200 w w w w + (680 w w w w || 100 nf) complex termination and hybrid balance r prog 63.4 k w pwr dc out i prog to test bus t ring t line t bat tip ring crowbar r pt 50 w r pr 50 w rring pr pt rtsp rtsp 2.0 m w c rts2 0.27 m f c rts1 0.022 m f r ts1 402 w r ts2 274 k w r tsn 2.0 m w v bat v ring 0.1 m f c bat1 bgnd v bat1 0.1 m f c dd dgnd v dd 0.1 m f c cc v cc agnd agnd c f1 c f2 c f1 0.47 m f 0.1 m f c f2 ntsd nstat b1 b0 0.1 m f c dd v dd agnd di cclk csel mclk timing and control ifs fsep sync d r d x pcm highway rcvn rcvp vtx 0.1 m f cb2 r tg 7.87 k w tg l8567 slic 1/4 T7507 codec fgnd r bat l7583 switch rtsn v bat2 vf r on vf r op vf x in tsd in test out inring in test in latch v bat2 rd1i rd2i rd3i do to l8567 en 0 en 1 en 2 en 3 b0 c b1 c nstat c ntsd c rd1 c rd2 c rd3 c ntsd0 en slic and l7583 switch 1, 2, or 3 to l8567 slic 1, 2, and 3 from l8567 slic 1, 2, and 3 to l7583b 1, 2, and 3 d x en c bat2 0.1 m f per channel common ntsd1 ntsd2 ntsd3 from l7583 1, 2, and 3 protector crowbar protector
lucent technologies inc. 29 data sheet august 1999 termination impedance, and hybrid balance T7507 quad pcm codec with filters, outline diagram 44-pin plcc controlling dimensions are in millimeters. note: the dimensions in this outline diagram are intended for informational purposes only. for detailed schemat- ics to assist your design efforts, please contact your lucent technologies sales representative. 5-2506r.8(f) 4.57 max 1.27 typ 0.53 max 0.10 seating plane 0.51 min typ 1 640 7 17 29 39 18 28 pin #1 identifier zone 16.66 max 17.65 max 16.66 max 17.65 max
l u cent t echn o logies i n c. re s e r v es t h e r i g ht t o ma k e chan g es to t he p r oduct ( s) o r in f o r m ation c o ntain e d he r ein with o ut no t i c e . n o liability i s assum e d as a res u l t of t h eir us e or applicatio n . no rights u nde r a n y pa t ent acc o mpa n y the s a l e of a n y such p r oduct ( s) o r in f o r m a tion. co p yright ? 199 9 luce n t t ec h nologie s inc. all rights res e r v ed a ugust 19 9 9 ds99 - 273alc (replaces d s 99-080 a lc) f o r a d d i ti o n a l i n fo r m a t i o n , c o n ta c t y o u r m i c r o e l e c t r o n i c s g r o u p a cc o u n t m a n a ge r o r t h e f o l l o wi n g: i n terne t : http://ww w . lucent.com/mic r o e-m a il: do c m a ste r @mi c r o .lu c ent. c om n. a m erica : microelectronics grou p , lucent t echnologies i nc., 555 union boul e v ard, room 30l-15 p -ba, allent o wn , p a 18103 1 - 80 0 - 37 2 - 2 4 4 7 , f a x 6 10 -7 1 2 - 4 1 06 ( i n c an a d a: 1 - 8 0 0 - 5 5 3 - 2 44 8 , f a x 6 1 0 - 71 2 - 4 1 06) asia p a cif i c : microelectronics grou p , lucent t echnologies singapore pt e . l t d. , 77 s cience p a r k d r i v e , #03-18 cintech iii , singa p o r e 1 1 82 5 6 t el. ( 65 ) 7 7 8 8 8 33 , f a x ( 6 5 ) 7 7 7 74 9 5 c h i n a: m i c r o e l e c t r o n i cs g r o u p , l u c e n t t e c hn o l o g i e s ( c h i na ) c o ., lt d ., a- f2 , 2 3 / f , za o f o n g u n i v e r s e b u i l d i n g , 18 0 0 zho n g s h a n x i r o a d , s h a ng h a i 2 00 2 3 3 p . r. c h i na t el. ( 86 ) 21 64 4 0 0 4 6 8 , ext . 316 , f a x ( 86 ) 21 64 4 0 0 6 5 2 j a p a n: m i c r o e l e c t r o n i cs g r o u p , l u c e n t t e c h n o l og i e s j ap a n l t d ., 7 - 1 8 , h i ga s h i - g o ta n d a 2 -c h o m e , s h i n a g a w a - k u , t o k y o 1 4 1, j a p an t el. ( 81 ) 3 5 42 1 1 6 0 0 , f a x ( 8 1 ) 3 5 4 2 1 17 0 0 e u r o p e : d at a r e qu e s t s : m ic r o e l e c t r o n ic s g r ou p d a t a li n e : t e l. ( 4 4 ) 7 00 0 5 8 2 36 8 , f a x ( 4 4 ) 1 1 8 9 3 2 8 148 t e c h n i cal i n q u i r i e s : ge r ma n y : ( 4 9 ) 8 9 9 50 8 6 0 (m u n i c h ) , u n i t e d ki n gdo m : ( 4 4 ) 1 3 44 86 5 9 0 0 (ascot), f r a n ce : ( 3 3 ) 1 4 0 8 3 6 8 0 0 (p a r i s), s we d e n : ( 4 6) 8 5 9 4 6 07 00 (sto c k h o l m) , fi n land : ( 3 5 8 ) 9 4 3 54 28 0 0 (h e ls i n k i), i t a l y : ( 3 9 ) 0 2 6 6 0 8 13 1 (m i l a n), s p ai n : ( 3 4 ) 1 8 0 7 1 4 4 1 (mad r id) d a t a s h e et a ugust 1999 t ermination impedanc e , and hybrid balance T7507 quad pcm codec with filters, o r dering in f ormation d e vic e p a r t no. description p a c k a g e c omcode t - 75 0 7 - - - ml 2 -d q u a d pcm co d e c (d r y-bag g ed) 44-pi n pl c c 10 8 49 6 704 t - 7 50 7 - - - m l2-dt qu a d pcm c o dec (d r y-b a gg e d, t a p e and reel) 44-pi n pl c c 10 8 49 6 712

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